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DRA7: fix ABB efuse offset for OPP_NOM
author
Nishanth Menon
<
[email protected]
>
Tue, 18 Feb 2014 18:00:01 +0000
(12:00 -0600)
committer
Tom Rini
<
[email protected]
>
Fri, 21 Feb 2014 18:55:41 +0000
(13:55 -0500)
commit
194dd74ad919e57026f385aaab7f89acf7ea79ef
(DRA7: add ABB setup for MPU voltage domain)
Made an offset typo error by using 0x4A003B24 as the efuse offset
for OPP_NOM. As per TI documentation, 0x4A003B24 is for OPP_OD, and
0x4A003B20 is for OPP_NOM. Fix the same.
Reported-by: Praveen Rao <
[email protected]
>
Signed-off-by: Nishanth Menon <
[email protected]
>
arch/arm/cpu/armv7/omap5/prcm-regs.c
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diff --git
a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index ff328070f77de8e85802c3563f70fcca68700b84..7292161f3cbd15a803673e622650dc5d1eb59e56 100644
(file)
--- a/
arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/
arch/arm/cpu/armv7/omap5/prcm-regs.c
@@
-432,7
+432,7
@@
struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_srcomp_code_latch = 0x4A002E84,
.control_ddr_control_ext_0 = 0x4A002E88,
.control_padconf_core_base = 0x4A003400,
- .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B2
4
,
+ .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B2
0
,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
.control_port_emif2_sdram_config = 0x4AE0C118,